Integrated circuit technology has been progressing rapidly to the point where integrated circuits incorporating over a million transistors are possible in such products as cell phones, radios, and TVs. However, the rapid development of technologies, which require such integrated circuits, has increased just as rapidly. Applications such as real-time graphics, high-definition television, virtual reality, and other scientific and industrial applications are demanding higher speed, greater functionality, and even more rapid advances in very large-scale integrated circuit technology.
The demand for more functionality requires a tremendous increase in the number of transistors to be integrated onto a single integrated circuit chip. This requires shrinking the sizes of the transistors and/or having larger die sizes.
As the sizes of the transistors decrease, the resulting increased density requires an increasing number of interconnections within the integrated circuit chip. As the number of interconnections increases, the amount of area on the semiconductor die occupied by the interconnections becomes relatively large and may offset the savings made by reducing the size of the transistors.
A long sought goal in the semiconductor industry for very large-scale integrated circuits has been to achieve minimum area layouts for interconnections because minimum area layouts typically provide optimum performance and economy.
In addition, as the number of transistors proliferate, multiple levels of interconnections are required between the interconnect lines and the vias which connect different levels.
At the present time, the vias are formed first and a via fill step is applied to protect the via bottom from early breakthrough while the dual damascene trench is being etched. This is called the “via-first” manufacturing process. Bottom anti-reflective coatings (BARC), of either organic or inorganic material, are commonly used to fill the vias.
As technology develops, low dielectric constant interlevel dielectric materials are required to reduce capacitance problems between the closer together interconnections in the smaller integrated circuits. However, the low dielectric constant materials cause problems in the via-first manufacturing process.
One of the process problems is that of resist poisoning during the dual damascene trench masking. Where the photoresist is poisoned, the dual damascene trench mask from which the trenches patterned are not well defined and the photoresist above the vias are not fully developed. This means that the interconnects may not be connected or thinner than designed so the resistance is higher and the likelihood of failure is higher.
Another of the process problems is the chemically related post-via processing, i.e., photoresist strip, wet cleaning, and via fill, which may also cause an undesirable change in the dielectric constant of the low dielectric constant material. This is especially true for porous ultra-low dielectric constant films.
A still further process problem as sizes continue to shrink is that it becomes more and more difficult to achieve robust and void-free BARC fill for smaller vias with the via-first process. This further causes problems in maintaining an acceptable process window during via masking with an appropriate resist thickness; i.e., having enough time to form the trench before breakthrough of the photoresist.
Solutions to these problems have been long sought, but have equally as long eluded those skilled in the art.